A New and Fast Approach to Very Large Scale Integrated Sequential Circuit Test Generation

J. B. Adams and D. S. Hochbaum
Additional contact information
J. B. Adams: The University of California, Berkeley, California
D. S. Hochbaum: The University of California, Berkeley, California

Operations Research, 1997, vol. 45, issue 6, 842-856

Abstract: We present a new approach to automatic test pattern generation for very large scale integrated sequential circuit testing. This approach is more efficient than past test generation methods, since it exploits knowledge of potential circuit defects. Our method motivates a new combinatorial optimization problem, the Tour Covering Problem . We develop heuristics to solve this optimization problem, then apply these heuristics as new test generation procedures. An empirical study comparing our heuristics to existing methods demonstrates the superiority of our approach, since our approach decreases the number of input vectors required for the test, translating into a reduction in the time and money required for testing sequential circuits.

Keywords: industry; computer electronic; semiconductor manufacturing; manufacturing performance/productivity; improved quality control by effective testing; programming integer heuristic; heuristic approach for the tour cover problem (search for similar items in EconPapers)
Date: 1997
References: Add references at CitEc
Citations:

Downloads: (external link)
http://dx.doi.org/10.1287/opre.45.6.842 (application/pdf)

Related works:
This item may be available elsewhere in EconPapers: Search for items with the same title.

Export reference: BibTeX RIS (EndNote, ProCite, RefMan) HTML/Text

Persistent link: https://EconPapers.repec.org/RePEc:inm:oropre:v:45:y:1997:i:6:p:842-856

Access Statistics for this article

More articles in Operations Research from INFORMS Contact information at EDIRC.
Bibliographic data for series maintained by Chris Asher ().