Digital Circuit Optimization via Geometric Programming

Stephen P. Boyd (), Seung-Jean Kim (), Dinesh D. Patil () and Mark A. Horowitz ()
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Stephen P. Boyd: Department of Electrical Engineering, Stanford University, Stanford, California 94305-9510
Seung-Jean Kim: Department of Electrical Engineering, Stanford University, Stanford, California 94305-9510
Dinesh D. Patil: Department of Electrical Engineering, Stanford University, Stanford, California 94305-9510
Mark A. Horowitz: Department of Electrical Engineering, Stanford University, Stanford, California 94305-9510

Operations Research, 2005, vol. 53, issue 6, 899-932

Abstract: This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

Keywords: programming: geometric; engineering: computer-aided design; digital circuit optimization (search for similar items in EconPapers)
Date: 2005
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Citations: View citations in EconPapers (16)

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