High-speed graphene transistors with a self-aligned nanowire gate

Lei Liao, Yung-Chen Lin, Mingqiang Bao, Rui Cheng, Jingwei Bai, Yuan Liu, Yongquan Qu, Kang L. Wang, Yu Huang and Xiangfeng Duan ()
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Lei Liao: University of California
Yung-Chen Lin: University of California
Mingqiang Bao: University of California
Rui Cheng: University of California
Jingwei Bai: University of California
Yuan Liu: University of California
Yongquan Qu: University of California
Kang L. Wang: University of California
Yu Huang: University of California
Xiangfeng Duan: University of California

Nature, 2010, vol. 467, issue 7313, 305-308

Abstract: Graphene transistors There is considerable interest in graphene for high-speed electronics applications because of its high carrier mobility, but conventional device-fabrication processes produce significant defects in the atomically thin carbon sheets that constitute graphene, severely degrading device performance. Liao et al. report a novel fabrication approach that circumvents such degradation by placing a nanowire, with a metallic core and insulating shell, on top of the graphene as a gate electrode. 'Source' and 'drain' electrodes are then deposited on graphene through a self-alignment process that causes no appreciable damage to the graphene lattice and preserves its high carrier mobility. This unique device layout ensures that the edges of the source, drain and gate electrodes are positioned precisely, enabling a transistor performance that is comparable in speed with the best existing devices of a similar size.

Date: 2010
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DOI: 10.1038/nature09405

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