Programmable nanowire circuits for nanoprocessors

Hao Yan, Hwan Sung Choe, SungWoo Nam, Yongjie Hu, Shamik Das (), James F. Klemic, James C. Ellenbogen and Charles M. Lieber ()
Additional contact information
Hao Yan: Harvard University
Hwan Sung Choe: Harvard University
SungWoo Nam: School of Engineering and Applied Sciences, Harvard University
Yongjie Hu: Harvard University
Shamik Das: Nanosystems Group, The MITRE Corporation
James F. Klemic: Nanosystems Group, The MITRE Corporation
James C. Ellenbogen: Nanosystems Group, The MITRE Corporation
Charles M. Lieber: Harvard University

Nature, 2011, vol. 470, issue 7333, 240-244

Abstract: Programmable nanowire nanoprocessor In a significant step forward in complexity and capability for bottom-up assembly of nanoelectronic circuits, Yan et al. demonstrate scalable and programmable logic tiles based on semiconductor nanowire transistor arrays. The same logic tile, consisting of 496 configurable transistor nodes in an area of about 960 square micrometres, can be programmed and operated as a full-adder or full-subtractor circuit, and used for various other functions including multiplexers. It should be possible in future to cascade these logic tiles to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Date: 2011
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DOI: 10.1038/nature09749

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