A III–V nanowire channel on silicon for high-performance vertical transistors

Katsuhiro Tomioka (), Masatoshi Yoshimura and Takashi Fukui
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Katsuhiro Tomioka: Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, Kita 13 Nishi 8, Sapporo 060-8628, Japan
Masatoshi Yoshimura: Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, Kita 13 Nishi 8, Sapporo 060-8628, Japan
Takashi Fukui: Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, Kita 13 Nishi 8, Sapporo 060-8628, Japan

Nature, 2012, vol. 488, issue 7410, 189-192

Abstract: The fabrication of transistors using vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate combines the advantages of a three-dimensional gate architecture with the high electron mobility of the III–V nanowires, drastically enhancing the on-state current and transconductance.

Date: 2012
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DOI: 10.1038/nature11293

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