A graph placement methodology for fast chip design

Azalia Mirhoseini (), Anna Goldie (), Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Azade Nova, Jiwoo Pak, Andy Tong, Kavya Srinivasa, William Hang, Emre Tuncer, Quoc V. Le, James Laudon, Richard Ho, Roger Carpenter and Jeff Dean
Additional contact information
Azalia Mirhoseini: Google Research, Brain Team, Google
Anna Goldie: Google Research, Brain Team, Google
Mustafa Yazgan: Google Chip Implementation and Infrastructure (CI2) Team, Google
Joe Wenjie Jiang: Google Research, Brain Team, Google
Ebrahim Songhori: Google Research, Brain Team, Google
Shen Wang: Google Research, Brain Team, Google
Young-Joon Lee: Google Chip Implementation and Infrastructure (CI2) Team, Google
Eric Johnson: Google Research, Brain Team, Google
Omkar Pathak: Google Chip Implementation and Infrastructure (CI2) Team, Google
Azade Nova: Google Research, Brain Team, Google
Jiwoo Pak: Google Chip Implementation and Infrastructure (CI2) Team, Google
Andy Tong: Google Chip Implementation and Infrastructure (CI2) Team, Google
Kavya Srinivasa: Google Chip Implementation and Infrastructure (CI2) Team, Google
William Hang: Stanford University
Emre Tuncer: Google Chip Implementation and Infrastructure (CI2) Team, Google
Quoc V. Le: Google Research, Brain Team, Google
James Laudon: Google Research, Brain Team, Google
Richard Ho: Google Chip Implementation and Infrastructure (CI2) Team, Google
Roger Carpenter: Google Chip Implementation and Infrastructure (CI2) Team, Google
Jeff Dean: Google Research, Brain Team, Google

Nature, 2021, vol. 594, issue 7862, 207-212

Abstract: Abstract Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area. To achieve this, we pose chip floorplanning as a reinforcement learning problem, and develop an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip. As a result, our method utilizes past experience to become better and faster at solving new instances of the problem, allowing chip design to be performed by artificial agents with more experience than any human designer. Our method was used to design the next generation of Google’s artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation. Finally, we believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields.

Date: 2021
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Citations: View citations in EconPapers (7)

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DOI: 10.1038/s41586-021-03544-w

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