A crossbar array of magnetoresistive memory devices for in-memory computing

Seungchul Jung, Hyungwoo Lee, Sungmeen Myung, Hyunsoo Kim, Seung Keun Yoon, Soon-Wan Kwon, Yongmin Ju, Minje Kim, Wooseok Yi, Shinhee Han, Baeseong Kwon, Boyoung Seo, Kilho Lee, Gwan-Hyeob Koh, Kangho Lee, Yoonjong Song, Changkyu Choi, Donhee Ham () and Sang Joon Kim ()
Additional contact information
Seungchul Jung: Samsung Electronics
Hyungwoo Lee: Samsung Electronics
Sungmeen Myung: Samsung Electronics
Hyunsoo Kim: Samsung Electronics
Seung Keun Yoon: Samsung Electronics
Soon-Wan Kwon: Samsung Electronics
Yongmin Ju: Samsung Electronics
Minje Kim: Samsung Electronics
Wooseok Yi: Samsung Electronics
Shinhee Han: Samsung Electronics
Baeseong Kwon: Samsung Electronics
Boyoung Seo: Samsung Electronics
Kilho Lee: Samsung Electronics
Gwan-Hyeob Koh: Samsung Electronics
Kangho Lee: Samsung Electronics
Yoonjong Song: Samsung Electronics
Changkyu Choi: Samsung Electronics
Donhee Ham: Samsung Electronics
Sang Joon Kim: Samsung Electronics

Nature, 2022, vol. 601, issue 7892, 211-216

Abstract: Abstract Implementations of artificial neural networks that borrow analogue techniques could potentially offer low-power alternatives to fully digital approaches1–3. One notable example is in-memory computing based on crossbar arrays of non-volatile memories4–7 that execute, in an analogue manner, multiply–accumulate operations prevalent in artificial neural networks. Various non-volatile memories—including resistive memory8–13, phase-change memory14,15 and flash memory16–19—have been used for such approaches. However, it remains challenging to develop a crossbar array of spin-transfer-torque magnetoresistive random-access memory (MRAM)20–22, despite the technology’s practical advantages such as endurance and large-scale commercialization5. The difficulty stems from the low resistance of MRAM, which would result in large power consumption in a conventional crossbar array that uses current summation for analogue multiply–accumulate operations. Here we report a 64 × 64 crossbar array based on MRAM cells that overcomes the low-resistance issue with an architecture that uses resistance summation for analogue multiply–accumulate operations. The array is integrated with readout electronics in 28-nanometre complementary metal–oxide–semiconductor technology. Using this array, a two-layer perceptron is implemented to classify 10,000 Modified National Institute of Standards and Technology digits with an accuracy of 93.23 per cent (software baseline: 95.24 per cent). In an emulation of a deeper, eight-layer Visual Geometry Group-8 neural network with measured errors, the classification accuracy improves to 98.86 per cent (software baseline: 99.28 per cent). We also use the array to implement a single layer in a ten-layer neural network to realize face detection with an accuracy of 93.4 per cent.

Date: 2022
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DOI: 10.1038/s41586-021-04196-6

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