Vertical MoS2 transistors with sub-1-nm gate lengths

Fan Wu, He Tian (), Yang Shen, Zhan Hou, Jie Ren, Guangyang Gou, Yabin Sun, Yi Yang and Tian-Ling Ren ()
Additional contact information
Fan Wu: Tsinghua University
He Tian: Tsinghua University
Yang Shen: Tsinghua University
Zhan Hou: Tsinghua University
Jie Ren: Tsinghua University
Guangyang Gou: Tsinghua University
Yabin Sun: East China Normal University
Yi Yang: Tsinghua University
Tian-Ling Ren: Tsinghua University

Nature, 2022, vol. 603, issue 7900, 259-264

Abstract: Abstract Ultra-scaled transistors are of interest in the development of next-generation electronic devices1–3. Although atomically thin molybdenum disulfide (MoS2) transistors have been reported4, the fabrication of devices with gate lengths below 1 nm has been challenging5. Here we demonstrate side-wall MoS2 transistors with an atomically thin channel and a physical gate length of sub-1 nm using the edge of a graphene layer as the gate electrode. The approach uses large-area graphene and MoS2 films grown by chemical vapour deposition for the fabrication of side-wall transistors on a 2-inch wafer. These devices have On/Off ratios up to 1.02 × 105 and subthreshold swing values down to 117 mV dec–1. Simulation results indicate that the MoS2 side-wall effective channel length approaches 0.34 nm in the On state and 4.54 nm in the Off state. This work can promote Moore’s law of the scaling down of transistors for next-generation electronics.

Date: 2022
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DOI: 10.1038/s41586-021-04323-3

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