High-κ perovskite membranes as insulators for two-dimensional transistors

Jing-Kai Huang (), Yi Wan, Junjie Shi, Ji Zhang, Zeheng Wang, Wenxuan Wang, Ni Yang, Yang Liu, Chun-Ho Lin, Xinwei Guan, Long Hu, Zi-Liang Yang, Bo-Chao Huang, Ya-Ping Chiu, Jack Yang, Vincent Tung, Danyang Wang, Kourosh Kalantar-Zadeh, Tom Wu, Xiaotao Zu, Liang Qiao, Lain-Jong Li () and Sean Li ()
Additional contact information
Jing-Kai Huang: University of New South Wales
Yi Wan: The University of Hong Kong
Junjie Shi: University of New South Wales
Ji Zhang: University of New South Wales
Zeheng Wang: University of New South Wales
Wenxuan Wang: University of New South Wales
Ni Yang: University of New South Wales
Yang Liu: University of New South Wales
Chun-Ho Lin: University of New South Wales
Xinwei Guan: University of New South Wales
Long Hu: University of New South Wales
Zi-Liang Yang: National Taiwan University
Bo-Chao Huang: National Taiwan University
Ya-Ping Chiu: National Taiwan University
Jack Yang: University of New South Wales
Vincent Tung: King Abdullah University of Science and Technology
Danyang Wang: University of New South Wales
Kourosh Kalantar-Zadeh: University of New South Wales
Tom Wu: University of New South Wales
Xiaotao Zu: School of Physics, University of Electronic Science and Technology of China
Liang Qiao: School of Physics, University of Electronic Science and Technology of China
Lain-Jong Li: The University of Hong Kong
Sean Li: University of New South Wales

Nature, 2022, vol. 605, issue 7909, 262-267

Abstract: Abstract The scaling of silicon metal–oxide–semiconductor field-effect transistors has followed Moore’s law for decades, but the physical thinning of silicon at sub-ten-nanometre technology nodes introduces issues such as leakage currents1. Two-dimensional (2D) layered semiconductors, with an atomic thickness that allows superior gate-field penetration, are of interest as channel materials for future transistors2,3. However, the integration of high-dielectric-constant (κ) materials with 2D materials, while scaling their capacitance equivalent thickness (CET), has proved challenging. Here we explore transferrable ultrahigh-κ single-crystalline perovskite strontium-titanium-oxide membranes as a gate dielectric for 2D field-effect transistors. Our perovskite membranes exhibit a desirable sub-one-nanometre CET with a low leakage current (less than 10−2 amperes per square centimetre at 2.5 megavolts per centimetre). We find that the van der Waals gap between strontium-titanium-oxide dielectrics and 2D semiconductors mitigates the unfavourable fringing-induced barrier-lowering effect resulting from the use of ultrahigh-κ dielectrics4. Typical short-channel transistors made of scalable molybdenum-disulfide films by chemical vapour deposition and strontium-titanium-oxide dielectrics exhibit steep subthreshold swings down to about 70 millivolts per decade and on/off current ratios up to 107, which matches the low-power specifications suggested by the latest International Roadmap for Devices and Systems5.

Date: 2022
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DOI: 10.1038/s41586-022-04588-2

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