Thousands of conductance levels in memristors integrated on CMOS

Mingyi Rao, Hao Tang, Jiangbin Wu, Wenhao Song, Max Zhang, Wenbo Yin, Ye Zhuo, Fatemeh Kiani, Benjamin Chen, Xiangqi Jiang, Hefei Liu, Hung-Yu Chen, Rivu Midya, Fan Ye, Hao Jiang, Zhongrui Wang, Mingche Wu, Miao Hu, Han Wang, Qiangfei Xia, Ning Ge, Ju Li and J. Joshua Yang ()
Additional contact information
Mingyi Rao: TetraMem
Hao Tang: Massachusetts Institute of Technology
Jiangbin Wu: University of Southern California
Wenhao Song: University of Southern California
Max Zhang: TetraMem
Wenbo Yin: TetraMem
Ye Zhuo: University of Southern California
Fatemeh Kiani: University of Massachusetts
Benjamin Chen: University of Massachusetts
Xiangqi Jiang: TetraMem
Hefei Liu: University of Southern California
Hung-Yu Chen: University of Southern California
Rivu Midya: University of Massachusetts
Fan Ye: University of Massachusetts
Hao Jiang: University of Massachusetts
Zhongrui Wang: University of Massachusetts
Mingche Wu: TetraMem
Miao Hu: TetraMem
Han Wang: University of Southern California
Qiangfei Xia: TetraMem
Ning Ge: TetraMem
Ju Li: Massachusetts Institute of Technology
J. Joshua Yang: TetraMem

Nature, 2023, vol. 615, issue 7954, 823-829

Abstract: Abstract Neural networks based on memristive devices1–3 have the ability to improve throughput and energy efficiency for machine learning4,5 and artificial intelligence6, especially in edge applications7–21. Because training a neural network model from scratch is costly in terms of hardware resources, time and energy, it is impractical to do it individually on billions of memristive neural networks distributed at the edge. A practical approach would be to download the synaptic weights obtained from the cloud training and program them directly into memristors for the commercialization of edge applications. Some post-tuning in memristor conductance could be done afterwards or during applications to adapt to specific situations. Therefore, in neural network applications, memristors require high-precision programmability to guarantee uniform and accurate performance across a large number of memristive networks22–28. This requires many distinguishable conductance levels on each memristive device, not only laboratory-made devices but also devices fabricated in factories. Analog memristors with many conductance states also benefit other applications, such as neural network training, scientific computing and even ‘mortal computing’25,29,30. Here we report 2,048 conductance levels achieved with memristors in fully integrated chips with 256 × 256 memristor arrays monolithically integrated on complementary metal–oxide–semiconductor (CMOS) circuits in a commercial foundry. We have identified the underlying physics that previously limited the number of conductance levels that could be achieved in memristors and developed electrical operation protocols to avoid such limitations. These results provide insights into the fundamental understanding of the microscopic picture of memristive switching as well as approaches to enable high-precision memristors for various applications.

Date: 2023
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DOI: 10.1038/s41586-023-05759-5

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