Synaptic and neural behaviours in a standard silicon transistor

Sebastian Pazos, Kaichen Zhu, Marco A. Villena, Osamah Alharbi, Wenwen Zheng, Yaqing Shen, Yue Yuan, Yue Ping and Mario Lanza ()
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Sebastian Pazos: King Abdullah University of Science and Technology (KAUST)
Kaichen Zhu: King Abdullah University of Science and Technology (KAUST)
Marco A. Villena: King Abdullah University of Science and Technology (KAUST)
Osamah Alharbi: King Abdullah University of Science and Technology (KAUST)
Wenwen Zheng: King Abdullah University of Science and Technology (KAUST)
Yaqing Shen: King Abdullah University of Science and Technology (KAUST)
Yue Yuan: King Abdullah University of Science and Technology (KAUST)
Yue Ping: King Abdullah University of Science and Technology (KAUST)
Mario Lanza: National University of Singapore

Nature, 2025, vol. 640, issue 8057, 69-76

Abstract: Abstract Hardware implementations of artificial neural networks (ANNs)—the most advanced of which are made of millions of electronic neurons interconnected by hundreds of millions of electronic synapses—have achieved higher energy efficiency than classical computers in some small-scale data-intensive computing tasks1. State-of-the-art neuromorphic computers, such as Intel’s Loihi2 or IBM’s NorthPole3, implement ANNs using bio-inspired neuron- and synapse-mimicking circuits made of complementary metal–oxide–semiconductor (CMOS) transistors, at least 18 per neuron and six per synapse. Simplifying the structure and size of these two building blocks would enable the construction of more sophisticated, larger and more energy-efficient ANNs. Here we show that a single CMOS transistor can exhibit neural and synaptic behaviours if biased in a specific (unconventional) manner. By connecting one additional CMOS transistor in series, we build a versatile 2-transistor-cell that exhibits adjustable neuro-synaptic response (which we named neuro-synaptic random access memory cell, or NS-RAM cell). This electronic performance comes with a yield of 100% and an ultra-low device-to-device variability, owing to the maturity of the silicon CMOS platform used—no materials or devices alien to the CMOS process are required. These results represent a short-term solution for the implementation of efficient ANNs and an opportunity in terms of CMOS circuit design and optimization for artificial intelligence applications.

Date: 2025
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DOI: 10.1038/s41586-025-08742-4

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