Using a diffusion wavelet neural network for short-term time series learning in the wafer level chip scale package process
Li Der-Chiang (),
Chun-Wu Yeh (),
Chieh-Chih Chen and
Hung-Ta Shih
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Li Der-Chiang: National Cheng Kung University
Chun-Wu Yeh: Kun Shan University
Chieh-Chih Chen: National Cheng Kung University
Hung-Ta Shih: National Cheng Kung University
Journal of Intelligent Manufacturing, 2016, vol. 27, issue 6, No 8, 1272 pages
Abstract:
Abstract Wafer level chip scale packages (WLCSP) have the advantages of high efficiency, high power and high density, and can ensure the consistent printed circuit board assembly necessary to achieve high yield and reliability. WLCSP are attracting more attention as electronic devices continue to become smaller and more portable. Although this package technology can enhance electronic signal input/output density, there is often the problem of a low yield in the early stage of its introduction. Several manufacturing factors influence the packaging process, with the height of the solder balls on multilayer metallic film being the decisive one. Due to the very few samples produced in pilot runs in the early stages of new product development, statistical process control charts can only provide limited information. This study is based on the idea of timeline division, and proposes a diffusion wavelet neural network which uses the correlated virtual sample generating method to improve its predictive performance for short-term time series. The diffusion wavelet neural network can improve the predictive accuracy more effectively than either a back-propagation neural network or a grey-based forecasting method.
Keywords: Short-term time series; Virtual samples; Wavelet neural network; Wafer level chip scale package (search for similar items in EconPapers)
Date: 2016
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DOI: 10.1007/s10845-014-0949-9
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