Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays

Abdessamad Ait El Cadi (), Omar Souissi, Rabie Ben Atitallah, Nicolas Belanger and Abdelhakim Artiba
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Abdessamad Ait El Cadi: UVHC - LAMIH CNRS UMR 8201
Omar Souissi: UVHC - LAMIH CNRS UMR 8201
Rabie Ben Atitallah: UVHC - LAMIH CNRS UMR 8201
Nicolas Belanger: Aéroport Marseille Provence
Abdelhakim Artiba: UVHC - LAMIH CNRS UMR 8201

Journal of Intelligent Manufacturing, 2018, vol. 29, issue 3, No 12, 629-640

Abstract: Abstract This paper deals with the mathematical modelling of a scheduling problem in a heterogeneous CPU/FPGA architecture with heterogeneous communication delays in order to minimize the makespan, $$C_{max}$$ C m a x . This study was motivated by the quality of the available solvers for Mixed Integer Program. The proposed model includes the communication delay constraints in a heterogeneous case, depending on both tasks and computing units. These constraints are linearized without adding any extra variables and the obtained linear model is reduced to speed-up the solving with CPLEX up to 60 times. Computational results show that the proposed model is promising. For an average sized problem of up to 50 tasks and five computing units the solving time under CPLEX is a few seconds.

Keywords: Heterogeneous system; Task scheduling; CPU/FPGA; Communication delays; Mixed Integer Program; CPLEX (search for similar items in EconPapers)
Date: 2018
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DOI: 10.1007/s10845-015-1075-z

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