An assignment-sequencing methodology for scheduling assembly and test operations with multi-pass requirements

Zhufeng Gao, Jonathan F. Bard, Rodolfo Chacon and John Stuber

IISE Transactions, 2015, vol. 47, issue 2, 153-172

Abstract: This article presents a three-phase methodology for scheduling assembly and test operations for semiconductor devices. The facility in which these operations are performed is a re-entrant flow shop consisting of several dozen to several hundred machines and up to a 1000 specialized tools. The semiconductor devices are contained in lots, and each lot follows a specific route through the facility, perhaps returning to the same machine multiple times. Each step in the route is referred to as a “pass.” In the first phase of the methodology an extended assignment model is solved to simultaneously assign tooling and lots to the machines. Four prioritized objectives are considered: minimize the weighted sum of key device shortages, maximize the weighted sum of lots processed, minimize the number of machines used, and minimize the makespan. In the second phase, lots are optimally sequenced on their assigned machines using the same prioritized objectives. Due to the precedent relations induced by the pass requirements, some lots may have to be delayed or removed from the assignment model solution to ensure that no machine runs beyond the planning horizon. In the third phase, machines are reset to allow additional lots to be processed when tooling is available. The methodology was tested using data provided by the Assembly and Test facility of a leading manufacturer. The results indicate that high-quality solutions can be obtained within 1 hour when compared with those obtained with a greedy randomized adaptive search procedure. Cost reductions were observed across all objectives and averaged 62% in the aggregate.

Date: 2015
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DOI: 10.1080/0740817X.2014.917778

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