TOTEM: A HIGHLY PARALLEL CHIP FOR TRIGGERING APPLICATIONS WITH INDUCTIVE LEARNING BASED ON THE REACTIVE TABU SEARCH

G. Anzellotti, R. Battiti, I. Lazzizzera, G. Soncini, A. Zorat, A. Sartori, G. Tecchiolli and P. Lee
Additional contact information
G. Anzellotti: Università di Trento, Trento, I-38100, Italy
R. Battiti: Università di Trento, Trento, I-38100, Italy
I. Lazzizzera: Università di Trento, Trento, I-38100, Italy
G. Soncini: Università di Trento, Trento, I-38100, Italy
A. Zorat: Università di Trento, Trento, I-38100, Italy
A. Sartori: Istituto per la Ricerca Scientifica e Tecnologica, Trento, I-38100, Italy
G. Tecchiolli: Istituto per la Ricerca Scientifica e Tecnologica, Trento, I-38100, Italy
P. Lee: University of Kent, Canterbury, CT2 7NQ, United Kingdom

International Journal of Modern Physics C (IJMPC), 1995, vol. 06, issue 04, 555-560

Abstract: The training of a Multi-Layer Perceptron (MLP) classifier is considered as a Combinatorial Optimization task and solved using the Reactive Tabu Search (RTS) method. RTS needs only forward passes (no derivatives) and does not require high precision network parameters. TOTEM, a special-purpose VLSI chip, was developed to take advantage of the limited memory and processing requirements of RTS: the final system effects a very close match between hardware and training algorithm. The RTS algorithm and the design of TOTEM are discussed, together with the operational characteristics of the VLSI chip and some preliminary training and generalization tests on triggering tasks.

Keywords: high energy physics; triggering; inductive learning; special purpose processors (search for similar items in EconPapers)
Date: 1995
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DOI: 10.1142/S0129183195000423

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