EXPERIENCE WITH THE IBM ZISC036 NEURAL NETWORK CHIP

Clark S. Lindsey (), Thomas Lindblad, Givi Sekhniaidze, G. Székely and M. Minerskjöld
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Clark S. Lindsey: Physics Dept. (Frescati), Royal Institute of Technology, Frescativägen 24, 104 05 Stockholm, Sweden
Thomas Lindblad: Physics Dept. (Frescati), Royal Institute of Technology, Frescativägen 24, 104 05 Stockholm, Sweden
Givi Sekhniaidze: Physics Dept. (Frescati), Royal Institute of Technology, Frescativägen 24, 104 05 Stockholm, Sweden
G. Székely: Physics Dept. (Frescati), Royal Institute of Technology, Frescativägen 24, 104 05 Stockholm, Sweden
M. Minerskjöld: Physics Dept. (Frescati), Royal Institute of Technology, Frescativägen 24, 104 05 Stockholm, Sweden

International Journal of Modern Physics C (IJMPC), 1995, vol. 06, issue 04, 579-584

Abstract: The new IBM Zero Instruction Set Computer (ZISC) provides a radial basis function neural network. The first generation chip (ZISC036) allows for 64 8-bit inputs, 36 RBF neurons in the middle layer, and up to 16383 possible output categories. Forward processing takes 4μs with a 20MHz clock. Cascading multiple chips increases the number of available RBF’s with no increase in processing time. The chip also executes a learning algorithm. We report on tests of the ZISC with a high energy physics related task.

Date: 1995
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DOI: 10.1142/S0129183195000460

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