Programming FPGAs for Economics: An Introduction to Electrical Engineering Economics

Bhagath Cheela, André DeHon, Jesus Fernandez-Villaverde and Alessandro Peri

No 29936, NBER Working Papers from National Bureau of Economic Research, Inc

Abstract: We show how to use field-programmable gate arrays (FPGAs) and their associated high-level synthesis (HLS) compilers to solve heterogeneous agent models with incomplete markets and aggregate uncertainty (Krusell and Smith, 1998). We document that the acceleration delivered by one single FPGA is comparable to that provided by using 74 CPU cores in a conventional cluster. We describe how to achieve multiple acceleration opportunities—pipeline, data-level parallelism, and data precision—with minimal modification of the C code written for a traditional sequential processor, which we then deploy on FPGAs easily available at Amazon Web Services. We quantify the speedup and cost of these accelerations. Our paper is the first step toward a new field, electrical engineering economics, focused on designing computational accelerators for economics to tackle challenging quantitative models.

JEL-codes: C60 C63 C88 D52 (search for similar items in EconPapers)
Date: 2022-04
New Economics Papers: this item is included in nep-cmp
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Working Paper: Programming FPGAs for Economics: An Introduction to Electrical Engineering Economics (2022)
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