CMOS Realization of All-Positive Pinched Hysteresis Loops

B. J. Maundy, A. S. Elwakil and C. Psychalinos

Complexity, 2017, vol. 2017, 1-15

Abstract:

Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.

Date: 2017
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Persistent link: https://EconPapers.repec.org/RePEc:hin:complx:7863095

DOI: 10.1155/2017/7863095

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