Probing single electrons across 300-mm spin qubit wafers

Samuel Neyens (), Otto K. Zietz, Thomas F. Watson, Florian Luthi, Aditi Nethwewala, Hubert C. George, Eric Henry, Mohammad Islam, Andrew J. Wagner, Felix Borjans, Elliot J. Connors, J. Corrigan, Matthew J. Curry, Daniel Keith, Roza Kotlyar, Lester F. Lampert, Mateusz T. Mądzik, Kent Millard, Fahd A. Mohiyaddin, Stefano Pellerano, Ravi Pillarisetty, Mick Ramsey, Rostyslav Savytskyy, Simon Schaal, Guoji Zheng, Joshua Ziegler, Nathaniel C. Bishop, Stephanie Bojarski, Jeanette Roberts and James S. Clarke ()
Additional contact information
Samuel Neyens: Intel Corp.
Otto K. Zietz: Intel Corp.
Thomas F. Watson: Intel Corp.
Florian Luthi: Intel Corp.
Aditi Nethwewala: Intel Corp.
Hubert C. George: Intel Corp.
Eric Henry: Intel Corp.
Mohammad Islam: Intel Corp.
Andrew J. Wagner: Intel Corp.
Felix Borjans: Intel Corp.
Elliot J. Connors: Intel Corp.
J. Corrigan: Intel Corp.
Matthew J. Curry: Intel Corp.
Daniel Keith: Intel Corp.
Roza Kotlyar: Intel Corp.
Lester F. Lampert: Intel Corp.
Mateusz T. Mądzik: Intel Corp.
Kent Millard: Intel Corp.
Fahd A. Mohiyaddin: Intel Corp.
Stefano Pellerano: Intel Corp.
Ravi Pillarisetty: Intel Corp.
Mick Ramsey: Intel Corp.
Rostyslav Savytskyy: Intel Corp.
Simon Schaal: Intel Corp.
Guoji Zheng: Intel Corp.
Joshua Ziegler: Intel Corp.
Nathaniel C. Bishop: Intel Corp.
Stephanie Bojarski: Intel Corp.
Jeanette Roberts: Intel Corp.
James S. Clarke: Intel Corp.

Nature, 2024, vol. 629, issue 8010, 80-85

Abstract: Abstract Building a fault-tolerant quantum computer will require vast numbers of physical qubits. For qubit technologies based on solid-state electronic devices1–3, integrating millions of qubits in a single processor will require device fabrication to reach a scale comparable to that of the modern complementary metal–oxide–semiconductor (CMOS) industry. Equally important, the scale of cryogenic device testing must keep pace to enable efficient device screening and to improve statistical metrics such as qubit yield and voltage variation. Spin qubits1,4,5 based on electrons in Si have shown impressive control fidelities6–9 but have historically been challenged by yield and process variation10–12. Here we present a testing process using a cryogenic 300-mm wafer prober13 to collect high-volume data on the performance of hundreds of industry-manufactured spin qubit devices at 1.6 K. This testing method provides fast feedback to enable optimization of the CMOS-compatible fabrication process, leading to high yield and low process variation. Using this system, we automate measurements of the operating point of spin qubits and investigate the transitions of single electrons across full wafers. We analyse the random variation in single-electron operating voltages and find that the optimized fabrication process leads to low levels of disorder at the 300-mm scale. Together, these results demonstrate the advances that can be achieved through the application of CMOS-industry techniques to the fabrication and measurement of spin qubit devices.

Date: 2024
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DOI: 10.1038/s41586-024-07275-6

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