A mixed-precision memristor and SRAM compute-in-memory AI processor

Win-San Khwa, Tai-Hao Wen, Hung-Hsi Hsu, Wei-Hsing Huang, Yu-Chen Chang, Ting-Chien Chiu, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Wei-Ting Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Ashwin Sanjay Lele, Shih-Hsin Teng, Chung-Cheng Chou, Yu- Der Chih, Tsung-Yung Jonathan Chang and Meng-Fan Chang ()
Additional contact information
Win-San Khwa: Taiwan Semiconductor Manufacturing Company Limited (TSMC)
Tai-Hao Wen: National Tsing Hua University (NTHU)
Hung-Hsi Hsu: Taiwan Semiconductor Manufacturing Company Limited (TSMC)
Wei-Hsing Huang: National Tsing Hua University (NTHU)
Yu-Chen Chang: National Tsing Hua University (NTHU)
Ting-Chien Chiu: National Tsing Hua University (NTHU)
Zhao-En Ke: National Tsing Hua University (NTHU)
Yu-Hsiang Chin: National Tsing Hua University (NTHU)
Hua-Jin Wen: National Tsing Hua University (NTHU)
Wei-Ting Hsu: National Tsing Hua University (NTHU)
Chung-Chuan Lo: National Tsing Hua University (NTHU)
Ren-Shuo Liu: National Tsing Hua University (NTHU)
Chih-Cheng Hsieh: National Tsing Hua University (NTHU)
Kea-Tiong Tang: National Tsing Hua University (NTHU)
Mon-Shu Ho: National Chung Hsing University (NCHU)
Ashwin Sanjay Lele: Taiwan Semiconductor Manufacturing Company Limited (TSMC)
Shih-Hsin Teng: Taiwan Semiconductor Manufacturing Company Limited (TSMC)
Chung-Cheng Chou: Taiwan Semiconductor Manufacturing Company Limited (TSMC)
Yu- Der Chih: Taiwan Semiconductor Manufacturing Company Limited (TSMC)
Tsung-Yung Jonathan Chang: Taiwan Semiconductor Manufacturing Company Limited (TSMC)
Meng-Fan Chang: Taiwan Semiconductor Manufacturing Company Limited (TSMC)

Nature, 2025, vol. 639, issue 8055, 617-623

Abstract: Abstract Artificial intelligence (AI) edge devices1–12 demand high-precision energy-efficient computations, large on-chip model storage, rapid wakeup-to-response time and cost-effective foundry-ready solutions. Floating point (FP) computation provides precision exceeding that of integer (INT) formats at the cost of higher power and storage overhead. Multi-level-cell (MLC) memristor compute-in-memory (CIM)13–15 provides compact non-volatile storage and energy-efficient computation but is prone to accuracy loss owing to process variation. Digital static random-access memory (SRAM)-CIM16–22 enables lossless computation; however, storage is low as a result of large bit-cell area and model loading is required during inference. Thus, conventional approaches using homogeneous CIM architectures and computation formats impose a trade-off between efficiency, storage, wakeup latency and inference accuracy. Here we present a mixed-precision heterogeneous CIM AI edge processor, which supports the layer-granular/kernel-granular partitioning of network layers among on-chip CIM architectures (that is, memristor-CIM, SRAM-CIM and tiny-digital units) and computation number formats (INT and FP) based on sensitivity to error. This layer-granular/kernel-granular flexibility allows simultaneous optimization within the two-dimensional design space at the hardware level. The proposed hardware achieved high energy efficiency (40.91 TFLOPS W−1 for ResNet-20 with CIFAR-100 and 28.63 TFLOPS W−1 for MobileNet-v2 with ImageNet), low accuracy degradation (

Date: 2025
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DOI: 10.1038/s41586-025-08639-2

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