Accurate and energy efficient ad-hoc neural network for wafer map classification

Ana Pinzari (), Thomas Baumela (), Liliana Andrade (), Maxime Martin (), Marcello Coppola () and Frédéric Pétrot ()
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Ana Pinzari: TIMA
Thomas Baumela: Elsys Design
Liliana Andrade: TIMA
Maxime Martin: STMicroelectronics
Marcello Coppola: STMicroelectronics
Frédéric Pétrot: TIMA

Journal of Intelligent Manufacturing, 2025, vol. 36, issue 4, No 32, 2863-2880

Abstract: Abstract Yield is key to profitability in semiconductor manufacturing and controlling the fabrication process is therefore a key duty for engineers in silicon foundries. Analyzing the distribution of the defective dies on a wafer is a necessary step to identify process shifts, and a major step in this analysis takes the form of a classification of these distributions on wafer bitmaps called wafer maps. Current approaches use large to huge state-of-the-art neural networks to perform this classification. We claim that given the task at hand, the use of much smaller, purpose defined neural networks is possible without much accuracy loss, while requiring two orders of magnitude less power than the current solutions. Our work uses actual foundry data from STMicroelectronics 28 nm fabrication facilities that it aims at classifying in 58 categories. We performed experiments using different low power boards for which we report accuracy, power consumption and power efficiency. As a result, we show that to classify 224 $$\times $$ × 224 wafer maps at foundry-throughput with an accuracy above 97% using a bit more than 1 W, is feasible.

Keywords: Semiconductor manufacturing; Advance process control; Wafer inspection; Convolutional neural networks; Low-power classification (search for similar items in EconPapers)
Date: 2025
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DOI: 10.1007/s10845-024-02390-7

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