Hardware Implementation of Floating-Point Arithmetic

Jean-Michel Muller (), Nicolas Brisebarre (), Florent de Dinechin (), Claude-Pierre Jeannerod (), Vincent Lefèvre (), Guillaume Melquiond (), Nathalie Revol (), Damien Stehlé () and Serge Torres ()
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Jean-Michel Muller: École Normale Supérieure de Lyon, CNRS, Laboratoire LIP
Nicolas Brisebarre: École Normale Supérieure de Lyon, CNRS, Laboratoire LIP
Florent de Dinechin: École Normale Supérieure de Lyon, ENSL, Laboratoire LIP
Claude-Pierre Jeannerod: École Normale Supérieure de Lyon, INRIA, Laboratoire LIP
Vincent Lefèvre: École Normale Supérieure de Lyon, INRIA, Laboratoire LIP
Guillaume Melquiond: Parc Orsay Université, INRIA Saclay – Île-de- France
Nathalie Revol: École Normale Supérieure de Lyon, INRIA, Laboratoire LIP
Damien Stehlé: Macquarie University, and University of Sydney School of Mathematics and Statistics University of Sydney, CNRS
Serge Torres: École Normale Supérieure de Lyon, ENSL, Laboratoire LIP

Chapter Chapter 9 in Handbook of Floating-Point Arithmetic, 2010, pp 269-320 from Springer

Abstract: Abstract The previous chapter has shown that operations on floating-point numbers are naturally expressed in terms of integer or fixed-point operations on the significand and the exponent. For instance, to obtain the product of two floating-point numbers, one basically multiplies the significands and adds the exponents. However, obtaining the correct rounding of the result may require considerable design effort and the use of nonarithmetic primitives such as leading-zero counters and shifters. This chapter details the implementation of these algorithms in hardware, using digital logic.

Keywords: Critical Path; Hardware Implementation; Close Path; Full Adder; Critical Path Delay (search for similar items in EconPapers)
Date: 2010
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DOI: 10.1007/978-0-8176-4705-6_9

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