Programming FPGAs for economics: An introduction to electrical engineering economics

Bhagath Cheela, André DeHon, Jesús Fernández‐Villaverde and Alessandro Peri

Quantitative Economics, 2025, vol. 16, issue 1, 49-87

Abstract: We show how to use field‐programmable gate arrays (FPGAs) and their associated high‐level synthesis (HLS) compilers to solve heterogeneous agent models with incomplete markets and aggregate uncertainty (Krusell and Smith (1998)). We document that the acceleration delivered by one single FPGA is comparable to that provided by using 69 CPU cores in a conventional cluster. The time to solve 1200 versions of the model drops from 8 hours to 7 minutes, illustrating a great potential for structural estimation. We describe how to achieve multiple acceleration opportunities—pipeline, data‐level parallelism, and data precision—with minimal modification of the C/C++ code written for a traditional sequential processor, which we then deploy on FPGAs easily available at Amazon Web Services. We quantify the speedup and cost of these accelerations. Our paper is the first step toward a new field, electrical engineering economics, focused on designing computational accelerators for economics to tackle challenging quantitative models. Replication code is available on Github.

Date: 2025
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